;buildInfoPackage: chisel3, version: 3.1.3, scalaVersion: 2.11.12, sbtVersion: 1.1.1, builtAtString: 2018-09-12 19:37:29.007, builtAtMillis: 1536781049007
circuit BubbleFifo : 
  module FifoRegister : 
    input clock : Clock
    input reset : UInt<1>
    output io : {enq : {flip write : UInt<1>, full : UInt<1>, flip din : UInt<8>}, deq : {flip read : UInt<1>, empty : UInt<1>, dout : UInt<8>}}
    
    reg stateReg : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[BubbleFifo.scala 51:25]
    reg dataReg : UInt<8>, clock with : (reset => (reset, UInt<8>("h00"))) @[BubbleFifo.scala 52:24]
    node _T_20 = eq(stateReg, UInt<1>("h00")) @[BubbleFifo.scala 54:17]
    when _T_20 : @[BubbleFifo.scala 54:28]
      when io.enq.write : @[BubbleFifo.scala 55:24]
        stateReg <= UInt<1>("h01") @[BubbleFifo.scala 56:16]
        dataReg <= io.enq.din @[BubbleFifo.scala 57:15]
        skip @[BubbleFifo.scala 55:24]
      skip @[BubbleFifo.scala 54:28]
    else : @[BubbleFifo.scala 59:33]
      node _T_21 = eq(stateReg, UInt<1>("h01")) @[BubbleFifo.scala 59:23]
      when _T_21 : @[BubbleFifo.scala 59:33]
        when io.deq.read : @[BubbleFifo.scala 60:23]
          stateReg <= UInt<1>("h00") @[BubbleFifo.scala 61:16]
          dataReg <= UInt<1>("h00") @[BubbleFifo.scala 62:15]
          skip @[BubbleFifo.scala 60:23]
        skip @[BubbleFifo.scala 59:33]
      else : @[BubbleFifo.scala 64:15]
        skip @[BubbleFifo.scala 64:15]
    node _T_23 = eq(stateReg, UInt<1>("h01")) @[BubbleFifo.scala 68:28]
    io.enq.full <= _T_23 @[BubbleFifo.scala 68:15]
    node _T_24 = eq(stateReg, UInt<1>("h00")) @[BubbleFifo.scala 69:29]
    io.deq.empty <= _T_24 @[BubbleFifo.scala 69:16]
    io.deq.dout <= dataReg @[BubbleFifo.scala 70:15]
    
  module FifoRegister_1 : 
    input clock : Clock
    input reset : UInt<1>
    output io : {enq : {flip write : UInt<1>, full : UInt<1>, flip din : UInt<8>}, deq : {flip read : UInt<1>, empty : UInt<1>, dout : UInt<8>}}
    
    reg stateReg : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[BubbleFifo.scala 51:25]
    reg dataReg : UInt<8>, clock with : (reset => (reset, UInt<8>("h00"))) @[BubbleFifo.scala 52:24]
    node _T_20 = eq(stateReg, UInt<1>("h00")) @[BubbleFifo.scala 54:17]
    when _T_20 : @[BubbleFifo.scala 54:28]
      when io.enq.write : @[BubbleFifo.scala 55:24]
        stateReg <= UInt<1>("h01") @[BubbleFifo.scala 56:16]
        dataReg <= io.enq.din @[BubbleFifo.scala 57:15]
        skip @[BubbleFifo.scala 55:24]
      skip @[BubbleFifo.scala 54:28]
    else : @[BubbleFifo.scala 59:33]
      node _T_21 = eq(stateReg, UInt<1>("h01")) @[BubbleFifo.scala 59:23]
      when _T_21 : @[BubbleFifo.scala 59:33]
        when io.deq.read : @[BubbleFifo.scala 60:23]
          stateReg <= UInt<1>("h00") @[BubbleFifo.scala 61:16]
          dataReg <= UInt<1>("h00") @[BubbleFifo.scala 62:15]
          skip @[BubbleFifo.scala 60:23]
        skip @[BubbleFifo.scala 59:33]
      else : @[BubbleFifo.scala 64:15]
        skip @[BubbleFifo.scala 64:15]
    node _T_23 = eq(stateReg, UInt<1>("h01")) @[BubbleFifo.scala 68:28]
    io.enq.full <= _T_23 @[BubbleFifo.scala 68:15]
    node _T_24 = eq(stateReg, UInt<1>("h00")) @[BubbleFifo.scala 69:29]
    io.deq.empty <= _T_24 @[BubbleFifo.scala 69:16]
    io.deq.dout <= dataReg @[BubbleFifo.scala 70:15]
    
  module FifoRegister_2 : 
    input clock : Clock
    input reset : UInt<1>
    output io : {enq : {flip write : UInt<1>, full : UInt<1>, flip din : UInt<8>}, deq : {flip read : UInt<1>, empty : UInt<1>, dout : UInt<8>}}
    
    reg stateReg : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[BubbleFifo.scala 51:25]
    reg dataReg : UInt<8>, clock with : (reset => (reset, UInt<8>("h00"))) @[BubbleFifo.scala 52:24]
    node _T_20 = eq(stateReg, UInt<1>("h00")) @[BubbleFifo.scala 54:17]
    when _T_20 : @[BubbleFifo.scala 54:28]
      when io.enq.write : @[BubbleFifo.scala 55:24]
        stateReg <= UInt<1>("h01") @[BubbleFifo.scala 56:16]
        dataReg <= io.enq.din @[BubbleFifo.scala 57:15]
        skip @[BubbleFifo.scala 55:24]
      skip @[BubbleFifo.scala 54:28]
    else : @[BubbleFifo.scala 59:33]
      node _T_21 = eq(stateReg, UInt<1>("h01")) @[BubbleFifo.scala 59:23]
      when _T_21 : @[BubbleFifo.scala 59:33]
        when io.deq.read : @[BubbleFifo.scala 60:23]
          stateReg <= UInt<1>("h00") @[BubbleFifo.scala 61:16]
          dataReg <= UInt<1>("h00") @[BubbleFifo.scala 62:15]
          skip @[BubbleFifo.scala 60:23]
        skip @[BubbleFifo.scala 59:33]
      else : @[BubbleFifo.scala 64:15]
        skip @[BubbleFifo.scala 64:15]
    node _T_23 = eq(stateReg, UInt<1>("h01")) @[BubbleFifo.scala 68:28]
    io.enq.full <= _T_23 @[BubbleFifo.scala 68:15]
    node _T_24 = eq(stateReg, UInt<1>("h00")) @[BubbleFifo.scala 69:29]
    io.deq.empty <= _T_24 @[BubbleFifo.scala 69:16]
    io.deq.dout <= dataReg @[BubbleFifo.scala 70:15]
    
  module FifoRegister_3 : 
    input clock : Clock
    input reset : UInt<1>
    output io : {enq : {flip write : UInt<1>, full : UInt<1>, flip din : UInt<8>}, deq : {flip read : UInt<1>, empty : UInt<1>, dout : UInt<8>}}
    
    reg stateReg : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[BubbleFifo.scala 51:25]
    reg dataReg : UInt<8>, clock with : (reset => (reset, UInt<8>("h00"))) @[BubbleFifo.scala 52:24]
    node _T_20 = eq(stateReg, UInt<1>("h00")) @[BubbleFifo.scala 54:17]
    when _T_20 : @[BubbleFifo.scala 54:28]
      when io.enq.write : @[BubbleFifo.scala 55:24]
        stateReg <= UInt<1>("h01") @[BubbleFifo.scala 56:16]
        dataReg <= io.enq.din @[BubbleFifo.scala 57:15]
        skip @[BubbleFifo.scala 55:24]
      skip @[BubbleFifo.scala 54:28]
    else : @[BubbleFifo.scala 59:33]
      node _T_21 = eq(stateReg, UInt<1>("h01")) @[BubbleFifo.scala 59:23]
      when _T_21 : @[BubbleFifo.scala 59:33]
        when io.deq.read : @[BubbleFifo.scala 60:23]
          stateReg <= UInt<1>("h00") @[BubbleFifo.scala 61:16]
          dataReg <= UInt<1>("h00") @[BubbleFifo.scala 62:15]
          skip @[BubbleFifo.scala 60:23]
        skip @[BubbleFifo.scala 59:33]
      else : @[BubbleFifo.scala 64:15]
        skip @[BubbleFifo.scala 64:15]
    node _T_23 = eq(stateReg, UInt<1>("h01")) @[BubbleFifo.scala 68:28]
    io.enq.full <= _T_23 @[BubbleFifo.scala 68:15]
    node _T_24 = eq(stateReg, UInt<1>("h00")) @[BubbleFifo.scala 69:29]
    io.deq.empty <= _T_24 @[BubbleFifo.scala 69:16]
    io.deq.dout <= dataReg @[BubbleFifo.scala 70:15]
    
  module BubbleFifo : 
    input clock : Clock
    input reset : UInt<1>
    output io : {enq : {flip write : UInt<1>, full : UInt<1>, flip din : UInt<8>}, deq : {flip read : UInt<1>, empty : UInt<1>, dout : UInt<8>}}
    
    inst FifoRegister of FifoRegister @[BubbleFifo.scala 81:43]
    FifoRegister.clock <= clock
    FifoRegister.reset <= reset
    inst FifoRegister_1 of FifoRegister_1 @[BubbleFifo.scala 81:43]
    FifoRegister_1.clock <= clock
    FifoRegister_1.reset <= reset
    inst FifoRegister_2 of FifoRegister_2 @[BubbleFifo.scala 81:43]
    FifoRegister_2.clock <= clock
    FifoRegister_2.reset <= reset
    inst FifoRegister_3 of FifoRegister_3 @[BubbleFifo.scala 81:43]
    FifoRegister_3.clock <= clock
    FifoRegister_3.reset <= reset
    FifoRegister_1.io.enq.din <= FifoRegister.io.deq.dout @[BubbleFifo.scala 83:31]
    node _T_17 = not(FifoRegister.io.deq.empty) @[BubbleFifo.scala 84:36]
    FifoRegister_1.io.enq.write <= _T_17 @[BubbleFifo.scala 84:33]
    node _T_18 = not(FifoRegister_1.io.enq.full) @[BubbleFifo.scala 85:31]
    FifoRegister.io.deq.read <= _T_18 @[BubbleFifo.scala 85:28]
    FifoRegister_2.io.enq.din <= FifoRegister_1.io.deq.dout @[BubbleFifo.scala 83:31]
    node _T_19 = not(FifoRegister_1.io.deq.empty) @[BubbleFifo.scala 84:36]
    FifoRegister_2.io.enq.write <= _T_19 @[BubbleFifo.scala 84:33]
    node _T_20 = not(FifoRegister_2.io.enq.full) @[BubbleFifo.scala 85:31]
    FifoRegister_1.io.deq.read <= _T_20 @[BubbleFifo.scala 85:28]
    FifoRegister_3.io.enq.din <= FifoRegister_2.io.deq.dout @[BubbleFifo.scala 83:31]
    node _T_21 = not(FifoRegister_2.io.deq.empty) @[BubbleFifo.scala 84:36]
    FifoRegister_3.io.enq.write <= _T_21 @[BubbleFifo.scala 84:33]
    node _T_22 = not(FifoRegister_3.io.enq.full) @[BubbleFifo.scala 85:31]
    FifoRegister_2.io.deq.read <= _T_22 @[BubbleFifo.scala 85:28]
    FifoRegister.io.enq.din <= io.enq.din @[BubbleFifo.scala 87:10]
    io.enq.full <= FifoRegister.io.enq.full @[BubbleFifo.scala 87:10]
    FifoRegister.io.enq.write <= io.enq.write @[BubbleFifo.scala 87:10]
    io.deq.dout <= FifoRegister_3.io.deq.dout @[BubbleFifo.scala 88:10]
    io.deq.empty <= FifoRegister_3.io.deq.empty @[BubbleFifo.scala 88:10]
    FifoRegister_3.io.deq.read <= io.deq.read @[BubbleFifo.scala 88:10]
    
